| Why Do Zigbee SOCs Have Such Little Resources? | | Print | |
| Written by Akiba | |
| Wednesday, 23 April 2008 | |
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An interesting question was asked in the forums which, although reworded, goes something like this: This is actually an interesting question and to answer it requires a bit of a background on IC design. Semiconductor hardware is all about cost, at least it is these days. The times are long gone when semiconductors was a glam industry. Consumer devices and PC products are all pushing down costs like crazy and the manufacturers are constantly pressuring the semiconductor suppliers to reduce their price. This is especially rampant in the standard products market, which includes the likes of ethernet, 802.11, and (if it takes off) 802.15.4 chips since they are all based on open standards. Chip costs are based on die size, that is, the area of silicon that is required to make the chip. That's where we'll start the analysis. For a standard Zigbee/802.15.4 SOC, the digital portion usually contains an 8-bit microcontroller, a set of peripherals like timers, UARTs, SPI, an 802.15.4 baseband controller, RAM, and flash. The silicon area of each component is calculated based on gate count, which is the number of equivalent gates that's required to implement the design. Here is a very rough estimate of the gate counts for the fixed size components I listed:
The reason I say fixed size is that RAM and flash can be variable, but you need the components listed above for the core functionality. My estimate is that the core functionality is about 40k gates. Actually, it's probably more like 50k +/- 10k gates because of miscellaneous logic as well. Now the job of the IC company is to minimize the cost of the IC, while making it appealing to the broadest customer base. Let's assume that the functional blocks are fixed and the appeal is determined by the flash and RAM size. RAM is expensive in the chip design world. 1 bit of RAM is the equivalent of 1.5 gates. This means that having 8 kB of RAM requires 64k RAM bits or 64k * 1.5 gates. Lets just say 8 kB of RAM uses 100k gates. That's huge in terms of the overall design, and already is twice the size of the functional logic. Flash is about one-fourth of the size of a logic gate or 0.25 gates. This is why the flash offering is usually larger than RAM. Let's say the minimum code size to implement a Zigbee stack is 100 kB. Usually, this means that you'd choose a flash size of 128 kB or 32k gates. So now, we can put everything together: Minimum size with no flash and RAM 50k gates (min size) Minimum size for a hypothetical Zigbee implementation (4 kB RAM, 64kB Flash) 50k + 50k + 16k = 116k gates (~2x min size) Optimal size for a Zigbee implementation with space left for application (8 kB RAM, 128 kB Flash) 50k + 100k + 32k = 182k gates (~3.5x min size) From the rough analysis above, you can see how the price is determined by the amount of resources. The fastest way to cut the price is to reduce RAM. Flash size reduction doesn't yield a very big cost benefit, but it's the only other tweakable factor for silicon die size. You can also see how a standalone radio like the CC2420 would be the most cost efficient unit-wise (but not BOM-wise). A standalone radio would probably be on the order of 30k gates or slightly more than half the minimum cost. There other ways to reduce the cost too, such as shrinking the process (0.18u to 0.13u). This results in a larger NRE, though. The NRE cost differential between the two processes is something like $100k for a set of 0.18u masks versus $400k for a set of 0.13u masks. I'm probably off on those numbers but you get the picture. The package is another way to cut cost. QFNs are cheap packages compared to SOIC and QFPs so that's why they're used a lot. Also, the smaller the die size and fewer pins, the smaller the QFN package it can be squeezed into. This also results in cost savings. All of these factors need to be balanced by the semiconductor supplier so that they can appeal to a wide audience without being undercut in price by their competitors. Normally, what happens is something like in the following diagram.
The blue line is the minimum RAM and Flash requirements to implement a Zigbee stack. The chip would be of little value if it couldn't implement basic Zigbee functionality. Anything above that is for performance enhancement and the end user application. The red line is the cost curve. It's a linear curve in this case, and it shows that as the resources (performance) increases, the cost will also increase. Semiconductor vendors tend to congregate towards the minimum cost to satisfy the requirements because they know that the biggest volume market will be at the lowest price points. These high volume/low price point markets are things like home automation and energy meters where they are price sensitive and don't require very sophisticated networks. Unfortunately, this also means that most of the chips will also have the least amount of resources needed to satisfy the largest amount of customers for these markets. This, in a slightly verbose form, is why most of the Zigbee SOC's on the market seem like they have very little resources. Hits: 485 Trackback(0)
Comments (2)
  written by Akiba, April 24, 2008
I'm not sure what the gate count is for EEPROMs, but I suspect they are similar to flash memory bits. The rule of thumb is flash mem is usually 1 transistor, a logic gate is 4 transistors, and SRAM is 6 transistors. Translated into gate counts (1 gate = 4T): flash = 0.25 gates, logic gate = 1 gate, RAM = 1.5 gates.
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thanks for the interesting cost evaluation of chip design ...
The first comments which pops out is what's the equivalency of a bit of EEPROM in terms of gates ?
The atmega128 has 4K EEPROM and IIRC msp430 used in telos motes has a similar amount of EEPROM ?
Does it matters in the final figure ?
Cheers
Aurélien